A 1.3 GSample/s 10-tap full-rate variable latency self-timed FIR filter with clocked interfaces
- Jose Tierno
- Alexander Rylyakov
- et al.
- 2002
- ISSCC 2002
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38 results for Sergey V. Rylov
A 1.3 Gsample/s 10-tap full-rate variable-latency self-timed FIR filter with clocked interfaces
- Jose Tierno
- Alexander Rylyakov
- et al.
- 2002
- ISSCC 2002
A 2.3GSample/s 10-tap digital FIR filter for magnetic recording read channels
- S. Rylov
- A. Rylyakov
- et al.
- 2001
- ISSCC 2001
A 32 Gb/s, 4.7 pJ/bit Optical Link With-11.7 dBm Sensitivity in 14-nm FinFET CMOS
- Jonathan E. Proesel
- Zeynep Toprak-Deniz
- et al.
- 2018
- IEEE JSSC
A 25 Gb/s Burst-Mode Receiver for Low Latency Photonic Switch Networks
- Alexander V. Rylyakov
- Jonathan E. Proesel
- et al.
- 2015
- IEEE JSSC
A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology
- Timothy O. Dickson
- Yong Liu
- et al.
- 2015
- IEEE JSSC
A 28-Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver in 32-nm SOI CMOS Technology
- John F. Bulzacchelli
- Christian Menolfi
- et al.
- 2012
- IEEE JSSC
A 16-Gb/s backplane transceiver with 12-tap current integrating DFE and dynamic adaptation of voltage offset and timing driftsin 45-nm SOI CMOS technology
- Gautam R. Gangasani
- Chun-Ming Hsu
- et al.
- 2012
- IEEE JSSC
A 32Gb/s, 4.7pJ/bit optical link with-11.7dBm sensitivity in 14nm FinFET CMOS
- Jonathan E. Proesel
- Zeynep Toprak-Deniz
- et al.
- 2017
- VLSI Circuits 2017
A 1.4-pJ/b, power-scalable 16×12-Gb/s source-synchronous I/O with DFE receiver in 32nm SOI CMOS technology
- Timothy O. Dickson
- Yong Liu
- et al.
- 2014
- CICC 2014