Integrated dual SPE processes with low contact resistivity for future CMOS technologies
- Heng Wu
- Soon-Cheon Seo
- et al.
- 2017
- IEDM 2017
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26 results for M. Sankarapandian
Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET
- N. Loubet
- T.B. Hook
- et al.
- 2017
- VLSI Technology 2017
A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels
- Ruilong Xie
- Pietro Montanini
- et al.
- 2016
- IEDM 2016
FINFET technology featuring high mobility SiGe channel for 10nm and beyond
- Dechao Guo
- G. Karve
- et al.
- 2016
- VLSI Technology 2016
TiN metal hard mask removal with selectivity to tungsten and TiN liner
- S. Lippy
- L. Chen
- et al.
- 2013
- ECS Transactions
56 nm pitch copper dual-damascene interconnects with triple pitch split metal and double pitch split via
- James Hsueh-Chung Chen
- Christopher Waskiewicz
- et al.
- 2012
- IITC 2012
Full metal gate with borderless contact for 14 nm and beyond
- Soon-Cheon Seo
- L.F. Edge
- et al.
- 2011
- VLSI Technology 2011
64 nm pitch Cu dual-damascene interconnects using pitch split double exposure patterning scheme
- Shyng-Tsong Chen
- Hideyuki Tomizawa
- et al.
- 2011
- IITC/MAM 2011
Systematic studies on reactive ion etch-induced deformations of organic underlayers
- Martin Glodde
- Sebastian Engelmann
- et al.
- 2011
- SPIE Advanced Lithography 2011
CoWP metal caps for reliable 32 nm 1X Cu interconnects in porous ULK (k=2.4)
- E. Huang
- M. Oh
- et al.
- 2009
- ADMETA 2009