Vertical-Transport Nanosheet Technology for CMOS Scaling beyond Lateral-Transport Devices
- H. Jagannathan
- B. Anderson
- et al.
- 2021
- IEDM 2021
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25 results for M. Sankarapandian
Multiple-Vt Solutions in Nanosheet Technology for High Performance and Low Power Applications
- Ruqiang Bao
- Reinaldo A. Vega
- et al.
- 2019
- IEDM 2019
Full Bottom Dielectric Isolation to Enable Stacked Nanosheet Transistor for Low Power and High Performance Applications
- J. Zhang
- S. Pancharatnam
- et al.
- 2019
- IEDM 2019
Integrated dual SPE processes with low contact resistivity for future CMOS technologies
- Heng Wu
- Soon-Cheon Seo
- et al.
- 2017
- IEDM 2017
A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels
- Ruilong Xie
- Pietro Montanini
- et al.
- 2016
- IEDM 2016
Nanoporous materials integration into advanced microprocessors
- E. Todd Ryan
- Cathy Labelle
- et al.
- 2005
- MRS Spring Meeting 2005
Resistive Memory Process Optimization for High Resistance Switching Toward Scalable Analog Compute Technology for Deep Learning
- Youngseok Kim
- Soon-Cheon Seo
- et al.
- 2021
- IEEE Electron Device Letters
An Evaluation of Bath Life Effects on Photoresist Removal for Wafer Level Packaging
- Joel A. Bahena
- Phillip Tyler
- et al.
- 2023
- Advancing Microelectronics
Manufacturing Yield Improvement for Advanced CMOS Technology Middle-of-Line Interconnect with Cobalt Metallization : YE: YieldEnhancement/Learning
- Susan Fan
- P. Jamison
- et al.
- 2023
- ASMC 2023
Parasitic Resistance Reduction for Aggressively Scaled Stacked Nanosheet Transistors
- Su-Chen Fan
- Ruilong Xie
- et al.
- 2020
- IITC 2020