Performance elements for 28nm gate length bulk devices with gate first high-k metal gate
- Jun Yuan
- C. Gruensfelder
- et al.
- 2010
- ICSICT 2010
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45 results for Rama Divakaruni
High-κ/metal gate low power bulk technology - Performance evaluation of standard CMOS logic circuits, microprocessor critical path replicas, and SRAM for 45nm and beyond
- D.-G. Park
- K. Stein
- et al.
- 2009
- VLSI-TSA 2009
Reduction of RTA-driven intra-die variation via model-based layout optimization
- J.C. Scott
- O. Gluschenkov
- et al.
- 2009
- VLSI Technology 2009
SMT and enhanced SPT with Recessed SD to improve CMOS Device Performance
- S. Fang
- S.S. Tan
- et al.
- 2008
- ICSICT 2008
A novel, low-cost deep trench decoupling capacitor for high-performance, low-power bulk CMOS applications
- Chengwen Pei
- Roger Booth
- et al.
- 2008
- ICSICT 2008
A 45nm low power bulk technology featuring carbon co-implantation and laser anneal on 45°-rotated substrate
- J. Yuan
- V. Chan
- et al.
- 2008
- ICSICT 2008
High-performance high-κ/metal gates for 45nm CMOS and beyond with gate-first processing
- M. Chudzik
- B. Doris
- et al.
- 2007
- VLSI Technology 2007
Body voltage and history effect sensitivity to key device parameters in 90nm PD-SOI
- S. Kawanaka
- M.B. Ketchen
- et al.
- 2004
- IEEE International SOI Conference 2004
On the retention time distribution of dual-channel vertical DRAM technologies
- J. Beintner
- Y. Li
- et al.
- 2003
- VLSI-TSA 2003
Characterization and Analysis of Random Telegraph Noise in Scaled SiGe Channel HKMG pMOSFETs
- Ch. L. N. Pavan
- Rama Divakaruni
- et al.
- 2022
- IEEE T-ED