Functional Testing of AI Cores through Thinned 3D I/O Buffer Dies in 3D Die-Stacked Modules
- Mukta Farooq
- Arvind Kumar
- et al.
- 2022
- ECTC 2022
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45 results for Rama Divakaruni
Characterization and Analysis of Random Telegraph Noise in Scaled SiGe Channel HKMG pMOSFETs
- Ch. L. N. Pavan
- Rama Divakaruni
- et al.
- 2022
- IEEE T-ED
Vertical-Transport Nanosheet Technology for CMOS Scaling beyond Lateral-Transport Devices
- H. Jagannathan
- B. Anderson
- et al.
- 2021
- IEDM 2021
Direct Bonded Heterogeneous Integration (DBHi) Si Bridge
- Kamal Sikka
- Ravi Bonam
- et al.
- 2021
- ECTC 2021
3-D Die Stacking with 55 μm Pitch Interconnections on Advanced Ground-Rule Laminate for Artificial Intelligence System
- Katsuyuki Sakuma
- Mukta Farooq
- et al.
- 2021
- IEEE Transactions on CPMT
Improved Air Spacer for Highly Scaled CMOS Technology
- Kangguo Cheng
- Chanro Park
- et al.
- 2020
- IEEE Transactions on Electron Devices
Improved Air Spacer Co-Integrated with Self-Aligned Contact (SAC) and Contact over Active Gate (COAG) for Highly Scaled CMOS Technology
- Kangguo Cheng
- Chanro Park
- et al.
- 2020
- VLSI Technology 2020
A Novel Dry Selective Etch of SiGe for the Enablement of High Performance Logic Stacked Gate-All-Around NanoSheet Devices
- Nicolas Loubet
- T. Devarajan
- et al.
- 2019
- IEDM 2019
Full Bottom Dielectric Isolation to Enable Stacked Nanosheet Transistor for Low Power and High Performance Applications
- J. Zhang
- S. Pancharatnam
- et al.
- 2019
- IEDM 2019
Extendable and Manufacturable Volume-less Multi-Vt Solution for 7nm Technology Node and beyond
- Ruqiang Bao
- Huimei Zhou
- et al.
- 2018
- IEDM 2018