A 3.0 TFLOPS 0.62V Scalable Processor Core for High Compute Utilization AI Training and Inference
- Jinwook Oh
- Sae Kyu Lee
- et al.
- 2020
- VLSI Circuits 2020
Publications
Date
Featured collections
Popular topics
19 results for George Gristede
A Scalable Multi-TeraOPS Deep Learning Processor Core for AI Trainina and Inference
- Bruce Fleischer
- Sunil Shukla
- et al.
- 2018
- VLSI Circuits 2018
A synthesis-parameter tuning system for autonomous design-space exploration
- Matt Ziegler
- Hung-Yi Liu
- et al.
- 2016
- DATE 2016
A scalable black-box optimization system for auto-tuning VLSI synthesis programs
- Matt Ziegler
- Hung-Yi Liu
- et al.
- 2016
- RES4ANT 2016
POWER8 design methodology innovations for improving productivity and reducing power
- Matthew M. Ziegler
- Ruchir Puri
- et al.
- 2014
- CICC 2014
Power reduction by aggressive synthesis design space exploration
- Matthew M. Ziegler
- George D. Gristede
- et al.
- 2013
- ISLPED 2013
The opportunity cost of low power design: A case study in circuit tuning
- Matthew M. Ziegler
- Victor V. Zyuban
- et al.
- 2009
- ISLPED 2009
Characterization of logic circuit techniques for high leakage CMOS technologies
- Phillip Chin
- Charles A. Zukowski
- et al.
- 2004
- GLSVLSI 2004
Mixed multi-threshold differential cascode voltage switch (MT-DCVS) circuit styles and strategies for low power VLSI design
- W. Chen
- W. Hwang
- et al.
- 2001
- ISLPED 2001
Comparison of dual-rail pass transistor logic families in 1.5 V, 0.18 μm CMOS technology for low power applications
- G.D. Gristede
- W. Hwang
- 2000
- GLSVLSI 2000