DiReC: Enhancing VHDL Code Generation and Summarization with Divide-Retrieve-Conquer Strategy
- Prashanth Vijayaraghavan
- Apoorva Nitsure
- et al.
- 2025
- DAC 2025
Publications
20 results for Charles Mackin
RTLExplain: A Structured Approach to RTL Code Summarization and Question Answering for Medium-to-Large Designs Using LLMs
- Ting-hsun (Austin) Chi
- Charles Mackin
- et al.
- 2025
- DAC 2025
Enhancing LLMs for HDL Code Optimization using Domain Knowledge Injection
- Che-ming Chang
- Prashanth Vijayaraghavan
- et al.
- 2025
- DAC 2025
Chain-of-Descriptions: Improving Code LLMs for VHDL Code Generation and Summarization
- Prashanth Vijayaraghavan
- Apoorva Nitsure
- et al.
- 2024
- MLCAD 2024
VHDL-Eval: A Framework for Evaluating Large Language Models in VHDL Code Generation
- Prashanth Vijayaraghavan
- Luyao Shi
- et al.
- 2024
- LAD 2024
Architecture and Programming of Analog In-Memory-Computing Accelerators for Deep Neural Networks
- Sidney Tsai
- Pritish Narayanan
- et al.
- 2024
- IPDPS 2024
Emerging Nonvolatile Memories for Analog Neuromorphic Computing
- An Chen
- Stefano Ambrogio
- et al.
- 2024
- ECS Spring Meeting 2024
Design of Analog-AI Hardware Accelerators for Transformer-based Language Models (Invited)
- Geoffrey Burr
- Sidney Tsai
- et al.
- 2023
- IEDM 2023
Using the IBM Analog In-Memory Hardware Acceleration Kit for Neural Network Training and Inference
- 2023
- APL Mach. Learn.
Phase Change Memory-based Hardware Accelerators for Deep Neural Networks
- Geoffrey Burr
- Pritish Narayanan
- et al.
- 2023
- VLSI Technology 2023