A 0.063 μm2 FinFET SRAM cell demonstration with conventional lithography using a novel integration scheme with aggressively scaled fin and gate pitch
- Veeraraghvan S. Basker
- Theodorus E. Standaert
- et al.
- 2010
- VLSI Technology 2010
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59 results for Hemanth Jagannathan
Optimizing band-edge high-κ/metal gate n-MOSFETs with ALD lanthanum oxide cap layers-oxidant and positioning effects
- Robert D. Clark
- H. Jagannathan
- et al.
- 2010
- ECS Transactions
Methodology of ALD HfO2 high-κ gate dielectric optimization by cyclic depositions and anneals
- H. Jagannathan
- Robert D. Clark
- et al.
- 2010
- ECS Transactions
Extremely scaled gate-first high-k/metal gate stack with EOT of 0.55 nm using novel interfacial layer scavenging techniques for 22nm technology node and beyond
- K. Choi
- H. Jagannathan
- et al.
- 2009
- VLSI Technology 2009
Engineering band-edge high-κ/metal gate n-MOSFETs with cap layers containing group IIA and IIIB elements by atomic layer deposition
- H. Jagannathan
- L.F. Edge
- et al.
- 2009
- ECS Meeting 2009
Engineering high dielectric constant materials for band-edge CMOS applications
- 2008
- ECS Meeting 2008
High-K gate dielectric structures by atomic layer deposition for the 32nm and beyond nodes
- R.D. Clark
- S. Consiglio
- et al.
- 2008
- ECS Meeting 2008
Vertical-Transport Nanosheet Technology for Scaling beyond the Lateral-Transport Devices CMOS Era
- Hemanth Jagannathan
- Susan Fan
- et al.
- 2023
- SSDM 2023
Next-Generation Logic Design Architecture for Vertical-Transport Nanosheets
- Biswanath (Biswa) Senapati
- Jeongho Do
- et al.
- 2023
- SPIE Advanced Lithography + Patterning 2023
High quality interfacial layer formation for Si0.75Ge0.25 (100) high-k metal gate stack
- S. Siddiqui
- R. Galatage
- et al.
- 2020
- Microelectronic Engineering