Stress migration reliability of copper interconnect stacked via structures with adjacent copper plates in low k- dielectrics
- D. Nguyen
- Kaushik Chanda
- et al.
- 2005
- VMIC 2005
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143 results for Daniel Edelstein
Lower-k SiCOH integration for 65 nm ground rules
- T. Nogami
- S. Lane
- et al.
- 2005
- VMIC 2005
Interconnect Issues post 45nm
- S.M. Rossnagel
- Robert L. Wisnieff
- et al.
- 2005
- IEDM 2005
Low-k/copper integration scheme suitable for ULSI manufacturing from 90nm to 45nm nodes
- T. Nogami
- S. Lane
- et al.
- 2005
- Optics East 2005
Silicon carrier with deep through-vias, fine pitch wiring, and through cavity for parallel optical transceiver
- Chirag S. Patel
- Cornelia K. Tsang
- et al.
- 2005
- ECTC 2005
Electrical and reliability evaluation of Cu/Low-k integration: Exploration of PVD barrier/seed and CVD SiC(N,H) cap depositions
- C.-C. Yang
- D. Edelstein
- et al.
- 2004
- ADMETA 2004
Low-k BEOL mechanical modeling
- Xiao Hu Liu
- Michael W. Lane
- et al.
- 2004
- ADMETA 2004
Optimization of SiCOH dielectrics for integration in a 90 nm CMOS technology
- A. Grill
- D. Edelstein
- et al.
- 2004
- IITC 2004
Chip-to-Package Interaction for a 90 nm Cu / PECVD Low-k technology
- W. Landers
- D. Edelstein
- et al.
- 2004
- IITC 2004
Channel cracking in low-k films on patterned multi-layers
- X.-H. Liu
- T.M. Shaw
- et al.
- 2004
- IITC 2004