High reliability 32 nm Cu/ULK BEOL based on PVD CuMn seed, and its extendibility
- Takeshi Nogami
- Tibor Bolom
- et al.
- 2010
- IEDM 2010
Publications
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143 results for Daniel Edelstein
A 45 nm CMOS node Cu/low-k/ ULtra low-k PECVD SiCOH (k=2.4) BEOL technology
- S. Sankaran
- S. Arai
- et al.
- 2006
- IEDM 2006
High performance 45-nm SOI technology with enhanced strain, porous low-k BEOL, and immersion lithography
- S. Narasimha
- K. Onishi
- et al.
- 2006
- IEDM 2006
Interconnect Issues post 45nm
- S.M. Rossnagel
- Robert L. Wisnieff
- et al.
- 2005
- IEDM 2005
Silicon carrier with deep through-vias, fine pitch wiring, and through cavity for parallel optical transceiver
- Chirag S. Patel
- Cornelia K. Tsang
- et al.
- 2005
- ECTC 2005
Functional high-speed characterization and modeling of a six-layer copper wiring structure and performance comparison with aluminum on-chip interconnections
- A. Deutsch
- H. Harrer
- et al.
- 1998
- IEDM 1998
RF circuit design aspects of spiral inductors on silicon
- J.N. Burghartz
- D. Edelstein
- et al.
- 1998
- ISSCC 1998
Full copper wiring in a sub-0.25 μm CMOS ULSI technology
- D. Edelstein
- J. Heidenreich
- et al.
- 1997
- IEDM 1997
Monolithic Spiral Inductors Fabricated Using a VLSI Cu-Damascene Interconnect Technology and Low-Loss Substrates
- J.N. Burghartz
- D. Edelstein
- et al.
- 1996
- IEDM 1996
Diamondlike carbon materials as low-k dielectrics for multilevel interconnects in ULSI
- A. Grill
- V.V. Patel
- et al.
- 1996
- MRS Fall Meeting 1996