Ruilong Xie, Pietro Montanini, et al.
IEDM 2016
Line resistance reduction in interconnects was achieved through Cu microstructure modulation. The modulation was performed via both raising annealing temperature and reducing the post-patterning dielectric aspect ratio and resulted in a bamboo-like Cu microstructure. Compared with the conventional polycrystalline, the modulated Cu microstructure also presents a lower resistivity increase rate with area scaling. A TaN stress control layer deposited on over-plated Cu surface was demonstrated to be critical for maintaining the Cu interconnect integrity after the high-temperature anneal.
Ruilong Xie, Pietro Montanini, et al.
IEDM 2016
Benjamin D. Briggs, C.B. Peethala, et al.
IEDM 2017
Son Van Nguyen, Hosadurga Shobha, et al.
VLSI-TSA 2020
H. Huang, Nicholas A. Lanzillo, et al.
IITC 2018