Gate-all-around silicon nanowire 25-stage CMOS ring oscillators with diameter down to 3 nm
- Sarunya Bangsaruntip
- A. Majumdar
- et al.
- 2010
- VLSI Technology 2010
Publications
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43 results for David P. Klaus
FinFET performance advantage at 22nm: An AC perspective
- M. Guillorn
- J. Chang
- et al.
- 2008
- VLSI Technology 2008
Reliability, yield, and performance of a 90 nm SOI/Cu/SiCOH technology
- D. Edelstein
- C.R. Davis
- et al.
- 2004
- IITC 2004
Optimization of SiCOH dielectrics for integration in a 90 nm CMOS technology
- A. Grill
- D. Edelstein
- et al.
- 2004
- IITC 2004
Comprehensive reliability evaluation of a 90 nm CMOS technology with Cu/PECVD low-k BEOL
- D. Edelstein
- H.S. Rathore
- et al.
- 2004
- IRPS 2004
Comprehensive reliability evaluation of a 90 nm CMOS technology with Cu/PECVD low-k BEOL
- D. Edelstein
- H.S. Rathore
- et al.
- 2004
- IRPS 2004
An optimal liner for copper damascene interconnects
- D. Edelstein
- C. Uzoh
- et al.
- 2001
- ADMETA 2001
Ultra-low power 0.1 μm CMOS
- Y. Mii
- S.J. Wind
- et al.
- 1994
- VLSI Technology 1994
Mixed e-beam/optical lithography process for the fabrication of sub-0.25-μm poly gates
- Keith T. Kwietniak
- Michael G. Rosenfield
- et al.
- 1993
- Microlithography 1993
A room temperature 0.1 μm CMOS on SOI
- G. Shahidi
- C. Blair
- et al.
- 1993
- VLSI Technology 1993