High performance 14nm SOI FinFET CMOS technology with 0.0174μm2 embedded DRAM and 15 levels of Cu metallization
- C.-H.C-H. Lin
- Brian Greene
- et al.
- 2014
- IEDM 2014
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8 results for Atsushi Ogino
ALD TaN barrier for enhanced performance with low contact resistance for 14 nm Technology Node Cu Interconnects
- Joyeeta Nag
- Brian A. Cohen
- et al.
- 2015
- ECS Meeting 2015 Phoenix
Strategy of Insertion of Merge Features in a Sea of Wires SADP Integration
- James H.-C. Chen
- Terry A. Spooner
- et al.
- 2018
- IITC 2018
High performance bulk planar 20nm CMOS technology for low power mobile applications
- Huiling Shang
- Sameer Jain
- et al.
- 2012
- VLSI Technology 2012
Moisture uptake impact on damage layer of porous low-k film in 80nm-pitched Cu interconnects
- M. Tagami
- Atsushi Ogino
- et al.
- 2011
- ECS Meeting 2011
Competitive and cost effective copper/low-k interconnect (BEOL) for 28nm CMOS technologies
- Rod Augur
- Craig Child
- et al.
- 2010
- ADMETA 2010
Application of E-beam hot spot inspection for early detection of systematic patterning problems to a FinFET technology
- Deborah A. Ryan
- Oliver D. Patterson
- et al.
- 2015
- J. Micro/Nanolithogr. MEMS MOEMS
Competitive and cost effective copper/low-k interconnect (BEOL) for 28 nm CMOS technologies
- R. Augur
- C. Child
- et al.
- 2012
- Microelectronic Engineering