Shiyi Chen, Daniel Martínez, et al.
Physics of Fluids
A cost effective 28 nm CMOS Interconnect technology is presented for 28 nm node high performance and low power applications. Full entitlement of ultra low-k (ULK) inter-level dielectric is enabled. Copper wiring levels can be combined up to a total of 11 levels. The inter-level dielectric was optimized for low k-value and high strength. The feature profiles were optimized to enable defect-free metallization using conventional tools and processes. High yields and robust reliability were demonstrated. © 2011 Elsevier B.V. All rights reserved.
Shiyi Chen, Daniel Martínez, et al.
Physics of Fluids
P. Martensson, R.M. Feenstra
Journal of Vacuum Science and Technology A: Vacuum, Surfaces and Films
Shu-Jen Han, Dharmendar Reddy, et al.
ACS Nano
William Hinsberg, Joy Cheng, et al.
SPIE Advanced Lithography 2010