A 1.4-pJ/b, power-scalable 16×12-Gb/s source-synchronous I/O with DFE receiver in 32nm SOI CMOS technology
- Timothy O. Dickson
- Yong Liu
- et al.
- 2014
- CICC 2014
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43 results for Lei Shan
Signal and power integrity (SPI) co-analysis for high-speed communication channels
- Renato Rimolo-Donadio
- Xiaomin Duan
- et al.
- 2013
- DesignCon 2013
Findings and considerations for I/O clock jitter on a source synchronous front side bus
- Daniel Dreps
- Len Daniels
- et al.
- 2012
- EPEPS 2012
Multi-level signaling in high-density, high-speed electrical links
- Dong G. Kam
- Troy J. Beukema
- et al.
- 2008
- DesignCon 2008
Comparison of bandwidth limits for on-card electrical and optical interconnects for 100 Gb/s and beyond
- Petar Pepeljugoski
- Mark Ritter
- et al.
- 2008
- SPIE IOPTO 2008
Signal propagation over perforated reference planes
- Lei Shan
- Mark Ritter
- et al.
- 2007
- IEEE-SPI 2007
Design, analysis and experimental verification of an equalized 10Gbps link
- Lei Shan
- Young Kwark
- et al.
- 2006
- DesignCon 2006
The use of fast integral equations solvers for practical package and interconnect analysis
- J.D. Morsey
- Barry J. Rubin
- et al.
- 2006
- IEEE Topical Meeting EPEPS 2006
Chip-to-chip optical interconnects
- J.A. Kash
- F.E. Doany
- et al.
- 2006
- OFC/NFOEC 2006
Terabus: A chip-to-chip parallel optical interconnect
- J.A. Kash
- F.E. Doany
- et al.
- 2005
- LEOS 2005