Evaluation of (110) versus (001) Channel Orientation for Improved nFET/pFET Device Performance Trade-Off in Gate-All-Around Nanosheet Technology
- Shogo Mochizuki
- Nicolas Loubet
- et al.
- 2023
- IEDM 2023
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27 results for Reinaldo A. Vega
Multiple-Vt Solutions in Nanosheet Technology for High Performance and Low Power Applications
- Ruqiang Bao
- Reinaldo A. Vega
- et al.
- 2019
- IEDM 2019
Full Bottom Dielectric Isolation to Enable Stacked Nanosheet Transistor for Low Power and High Performance Applications
- J. Zhang
- S. Pancharatnam
- et al.
- 2019
- IEDM 2019
Channel Geometry Impact and Narrow Sheet Effect of Stacked Nanosheet
- Chun Wing Yeung
- Jingyun Zhang
- et al.
- 2018
- IEDM 2018
Technology viable DC performance elements for Si/SiGe channel CMOS FinFTT
- G. Tsutsui
- Ruqiang Bao
- et al.
- 2016
- IEDM 2016
High performance 14nm SOI FinFET CMOS technology with 0.0174μm2 embedded DRAM and 15 levels of Cu metallization
- C.-H.C-H. Lin
- Brian Greene
- et al.
- 2014
- IEDM 2014
Accurate Modeling of Cryogenic Temperature Effects in 10-nm Bulk CMOS FinFETs Using the BSIM-CMG Model
- Sujit K. Singh
- Sumreti Gupta
- et al.
- 2022
- IEEE Electron Device Letters
Evaluation of 10-nm Bulk FinFET RF Performance - Conventional Versus NC-FinFET
- R. Singh
- K. Aditya
- et al.
- 2018
- IEEE Electron Device Letters
Methodology Development to Benchmark Power Delivery Designs in Advanced Technology Nodes
- Nicholas A. Lanzillo
- A. Chu
- et al.
- 2023
- SPIE Advanced Lithography + Patterning 2023
Impact of LER on Mismatch in Nanosheet Transistors for 5nm-CMOS
- Chandan Kumar Jha
- Charu Gupta
- et al.
- 2020
- EDTM 2020