Impact of LER on Mismatch in Nanosheet Transistors for 5nm-CMOS
- Chandan Kumar Jha
- Charu Gupta
- et al.
- 2020
- EDTM 2020
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28 results for Reinaldo A. Vega
Comparison of LER induced mismatch in NWFET and NSFET for 5-nm CMOS
- Chandan Kumar Jha
- Pritam Yogi
- et al.
- 2020
- IEEE J-EDS
Chip Power-Frequency Scaling in 10/7nm Node
- Phil Oldiges
- Reinaldo A. Vega
- et al.
- 2020
- IEEE Access
Full Bottom Dielectric Isolation to Enable Stacked Nanosheet Transistor for Low Power and High Performance Applications
- J. Zhang
- S. Pancharatnam
- et al.
- 2019
- IEDM 2019
Multiple-Vt Solutions in Nanosheet Technology for High Performance and Low Power Applications
- Ruqiang Bao
- Reinaldo A. Vega
- et al.
- 2019
- IEDM 2019
Impact of Hot Carrier Stress on RF FOMs in 10-nm Bulk N-Channel FinFETs
- Anshul Gupta
- Charu Gupta
- et al.
- 2019
- IIRW 2019
Reliability Modeling and Analysis of Hot-Carrier Degradation in Multiple-Fin SOI n-Channel FinFETs With Self-Heating
- Anshul Gupta
- Charu Gupta
- et al.
- 2019
- IEEE T-ED
Evaluation of 10-nm Bulk FinFET RF Performance - Conventional Versus NC-FinFET
- R. Singh
- K. Aditya
- et al.
- 2018
- IEEE Electron Device Letters
Channel Geometry Impact and Narrow Sheet Effect of Stacked Nanosheet
- Chun Wing Yeung
- Jingyun Zhang
- et al.
- 2018
- IEDM 2018
Technology viable DC performance elements for Si/SiGe channel CMOS FinFTT
- G. Tsutsui
- Ruqiang Bao
- et al.
- 2016
- IEDM 2016