Publications

25 results for Michael Belyansky

SMT and enhanced SPT with Recessed SD to improve CMOS Device Performance
- - S. Fang
  - S.S. Tan
  - et al.
- 2008
- ICSICT 2008
High performance 45-nm SOI technology with enhanced strain, porous low-k BEOL, and immersion lithography
- - S. Narasimha
  - K. Onishi
  - et al.
- 2006
- IEDM 2006
Stress proximity technique for performance improvement with dual stress liner at 45nm technology and beyond
- - X. Chen
  - S. Fang
  - et al.
- 2006
- VLSI Technology 2006
High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell
- - E. Leobandung
  - H. Nayakama
  - et al.
- 2005
- VLSI Technology 2005
Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing
- - H.S. Yang
  - R. Malik
  - et al.
- 2004
- IEDM 2004