High performance extremely thin SOI (ETSOI) hybrid CMOS with Si channel NFET and strained SiGe channel PFET
- K. Cheng
- A. Khakifirooz
- et al.
- 2012
- IEDM 2012
Publications
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80 results for Robert Dennard
Technologies to further reduce soft error susceptibility in SOI
- P. Oldiges
- R.H. Dennard
- et al.
- 2009
- IEDM 2009
1GHz fully pipelined 3.7ns Address access time 8kx1024 embedded DRAM macro
- O. Takahashi
- S. Dhong
- et al.
- 2000
- ISSCC 2000
When are transmission-line effects important for on-chip interconnections
- A. Deutsch
- G.V. Kopcsay
- et al.
- 1997
- ECTC 1997
Channel profile optimization and device design for low-power high-performance dynamic-threshold MOSFET
- Clement Wann
- Fariborz Assaderaghi
- et al.
- 1996
- IEDM 1996
SOI for a 1-Volt CMOS Technology and Application to a 512kb SRAM with 3.5 ns Access Time
- G. Shahidi
- T.H. Ning
- et al.
- 1993
- IEDM 1993
EXPERIMENTAL TECHNOLOGY AND CHARACTERIZATION OF SELF-ALIGNED 0. 1 mu M-GATE-LENGTH LOW-TEMPERATURE OPERATION NMOS DEVICES.
- G.A. Sai-Halasz
- M.R. Wordeman
- et al.
- 1986
- IEDM 1986
0. 5- mu M-CHANNEL CMOS TECHNOLOGY OPTIMIZED FOR LIQUID-NITROGEN-TEMPERATURE OPERATION.
- J.Y.-C. Sun
- Y. Taur
- et al.
- 1985
- IEDM 1985
CHARACTERIZATION AND MODELING OF A LATCHUP-FREE 1- mu M CMOS TECHNOLOGY.
- Y. Taur
- W.H. Chang
- et al.
- 1983
- IEDM 1983
An experimental high-density memory array fabricated with electron beam
- H.N. Yu
- R.H. Dennard
- et al.
- 1973
- ISSCC 1973