Advanced FDSOI design: The U-channel device for 7nm node and beyond
- Ramachandran Muralidhar
- Robert Dennard
- et al.
- 2017
- S3S 2017
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80 results for Robert Dennard
Advanced FDSOI Device Design: The U-Channel Device for 7 nm Node and beyond
- Ramachandran Muralidhar
- Robert Dennard
- et al.
- 2018
- IEEE J-EDS
High-performance Si1-xGex channel on insulator trigate PFETs featuring an implant-free process and aggressively-scaled fin and gate dimensions
- P. Hashemi
- M. Kobayashi
- et al.
- 2013
- VLSI Circuits 2013
High-performance Si1-xGex channel on insulator trigate PFETs featuring an implant-free process and aggressively-scaled fin and gate dimensions
- P. Hashemi
- M. Kobayashi
- et al.
- 2013
- VLSI Technology 2013
High performance extremely thin SOI (ETSOI) hybrid CMOS with Si channel NFET and strained SiGe channel PFET
- K. Cheng
- A. Khakifirooz
- et al.
- 2012
- IEDM 2012
A fully-integrated switched-capacitor 2:1 Voltage converter with regulation capability and 90% efficiency at 2.3A/mm2
- Leland Chang
- Robert K. Montoye
- et al.
- 2010
- VLSI Circuits 2010
FDSOI CMOS with dielectrically-isolated back gates and 30nm LG high-κ/metal gate
- Marwan Khater
- J. Cai
- et al.
- 2010
- VLSI Technology 2010
Practical strategies for power-efficient computing technologies
- Leland Chang
- David J. Frank
- et al.
- 2010
- Proceedings of the IEEE
Technologies to further reduce soft error susceptibility in SOI
- P. Oldiges
- R.H. Dennard
- et al.
- 2009
- IEDM 2009
FDSOI CMOS with dual backgate control for performance and power modulation
- Jeng-Bang Yau
- Jin Cai
- et al.
- 2009
- VLSI-TSA 2009