Manipulating Surface States of III-V Nanowires with Uniaxial Stress
- Giorgio Signorello
- Saurabh Sant
- et al.
- 2017
- Nano Letters
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18 results for Saurabh Sant
III-V heterojunction nanowire tunnel FETs monolithically integrated on silicon
- Kirsten E. Moselund
- D. Cutaia
- et al.
- 2016
- NMDC 2016
Lateral InAs/Si p-Type Tunnel FETs Integrated on Si - Part 2: Simulation Study of the Impact of Interface Traps
- Saurabh Sant
- Kirsten E. Moselund
- et al.
- 2016
- IEEE T-ED
Lateral InAs/Si p-Type Tunnel FETs Integrated on Si - Part 1: Experimental Devices
- Kirsten E. Moselund
- D. Cutaia
- et al.
- 2016
- IEEE T-ED
Complementary III-V heterostructure tunnel FETs
- Kirsten E. Moselund
- D. Cutaia
- et al.
- 2016
- ESSDERC 2016
Impact of trap-assisted tunneling and channel quantization on InAs/Si hetero Tunnel FETs
- Saurabh Sant
- Andreas Schenk
- et al.
- 2016
- DRC 2016
III-V-based hetero tunnel FETs: A simulation study with focus on non-ideality effects
- Andreas Schenk
- Saurabh Sant
- et al.
- 2016
- EUROSOI-ULIS 2016
Comparative simulation study of InAs/Si and All-III-V hetero tunnel FETs
- Andreas Schenk
- Saurabh Sant
- et al.
- 2015
- ECS Meeting 2015 Chicago