ETSOI CMOS for system-on-chip applications featuring 22nm gate length, sub-100nm gate pitch, and 0.08μm2 SRAM cell
- Kangguo Cheng
- A. Khakifirooz
- et al.
- 2011
- VLSI Technology 2011
Publications
Date
Featured collections
Popular topics
40 results for Steven J. Holmes
Optimization of pitch-split double patterning phoresist for applications at the 16nm node
- Steven J. Holmes
- Cherry Tang
- et al.
- 2011
- ASMC 2011
Self-assembly patterning for sub-15nm half-pitch: A transition from lab to fab
- Chris Bencher
- Jeffrey Smith
- et al.
- 2011
- SPIE Advanced Lithography 2011
Optimization of pitch-split double patterning photoresist for applications at the 16nm node
- Steven J. Holmes
- Cherry Tang
- et al.
- 2011
- SPIE Advanced Lithography 2011
Critical challenges for "non-critical" layers
- J.M. Gomez
- I.Y. Popova
- et al.
- 2011
- SPIE Advanced Lithography 2011
Challenges and opportunities of extremely thin SOI (ETSOI) CMOS technology for future low power and general purpose system-on-chip applications
- A. Khakifirooz
- Kangguo Cheng
- et al.
- 2010
- VLSI-TSA 2010
A 0.063 μm2 FinFET SRAM cell demonstration with conventional lithography using a novel integration scheme with aggressively scaled fin and gate pitch
- Veeraraghvan S. Basker
- Theodorus E. Standaert
- et al.
- 2010
- VLSI Technology 2010
Integration of directed self-assembly with 193 nm lithography
- Daniel P. Sanders
- Joy Cheng
- et al.
- 2010
- J. Photopolym. Sci. Tech.
Simple and versatile methods to integrate directed self-assembly with optical lithography using a polarity-switched photoresist
- Joy Y. Cheng
- Daniel P. Sanders
- et al.
- 2010
- ACS Nano
Fabrication of dual damascene BEOL structures using a multi-level multiple exposure (MLME) scheme - Part 2. RIE-based pattern transfer and completion of dual damascene process yielding an electrically functional via chain
- Stefan Harrer
- John C Arnold
- et al.
- 2010
- Proceedings of SPIE - The International Society for Optical Engineering 2010