Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing
- H.S. Yang
- R. Malik
- et al.
- 2004
- IEDM 2004
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36 results for Shreesh Narasimha
Performance enhancement on sub-70 nm strained silicon SOI MOSFETS on ultra-thin thermally mixed strained silicon/SiGe on insulator(TM-SGOI) substrate with raised S/D
- B.H. Lee
- A.C. Mocuta
- et al.
- 2002
- IEDM 2002
A high performance 90 nm SOI technology with 0.992 μm2 6T-SRAM cell
- Mukesh Khare
- S. Ku
- et al.
- 2002
- IEDM 2002
Low field mobility characteristics of sub-100 nm unstrained and strained Si MOSFETs
- K. Rim
- S. Narasimha
- et al.
- 2002
- IEDM 2002
Gate-dielectric permitivity and metal-gate work-function tradeoff in Lmet = 25 nm PDSOI device characteristics
- Dechao Guo
- Andres Bryant
- et al.
- 2006
- IEEE Electron Device Letters
Segment removal strategy in SAQP for advanced BEOL application
- James H.-C. Chen
- Terry A. Spooner
- et al.
- 2017
- IITC 2017
Planarity considerations in SADP for advanced BEOL patterning
- James H.-C. Chen
- Terry A. Spooner
- et al.
- 2017
- IITC 2017
A novel ALD SiBCN low-k spacer for parasitic capacitance reduction in FinFETs
- Tenko Yamashita
- S. Mehta
- et al.
- 2015
- VLSI Technology 2015
22nm technology yield optimization using multivariate 3D virtual fabrication
- B. Cipriany
- B. Jagannathan
- et al.
- 2013
- SISPAD 2013
Deposited ALD SiO2 high-k/metal gate interface for high voltage analog and I/O devices on next generation alternative channels and FINFET device structures
- S. Siddiqui
- M.M. Chowdhury
- et al.
- 2013
- ECS Meeting 2013