Channel strain engineering for high performance CMOS technology
Hasan M. Nayfeh
RTP 2008
Lateral asymmetric channel doping is applied to 45-nm technology NFET devices. The measured effective draincurrent enhancement over coprocessed symmetric control devices is 10%. Analysis reveals that the dominant physical mechanism, which accounts for two-third of the total enhanced drain current, is an 8% increase in the source-side injection velocity. The remaining one-third is attributed to the decreased drain-induced barrier lowering. This paper concludes with an analysis of the switching characteristics of CMOS inverters composed of an asymmetric NFET and a companion symmetric PFET and shows a 5% improvement in the delay. The improvement is explained in terms of the increased velocity and 30% reduction in drain junction capacitance. © 2009 IEEE.
Hasan M. Nayfeh
RTP 2008
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