Addressing test generation challenges for configurable processor verification
- M. Rimon
- Yossi Lichtenstein
- et al.
- 2006
- HLDVT 2006
Publications
Date
Featured collections
Popular topics
21 results for Allon Adir
Extending the model-based approach to functional verification of address translation mechanisms
- Allon Adir
- Laurent Fournier
- et al.
- 2006
- HLDVT 2006
VLIW - A case study of parallelism verification
- Allon Adir
- Yaron Arbetman
- et al.
- 2005
- DAC 2005
A generic micro-architectural test plan approach for microprocessor verification
- Allon Adir
- Hezi Azatchi
- et al.
- 2005
- DAC 2005
Genesys-Pro: Innovations in test program generation for functional processor verification
- Allon Adir
- Eli Almog
- et al.
- 2004
- IEEE Design and Test of Computers
Piparazzi: A test program generator for micro-architecture flow verification
- A. Adir
- E. Bin
- et al.
- 2003
- HLDVT 2003
DeepTrans - A model-based approach to functional verification of address translation mechanisms
- A. Adir
- R. Emek
- et al.
- 2003
- MTV 2003
Information-flow models for shared memory with an application to the PowerPC architecture
- Allon Adir
- Hagit Attiya
- et al.
- 2003
- IEEE TPDS
Generating concurrent test-programs with collisions for multi-processor verification
- A. Adir
- Gil Shurek
- 2002
- HLDVT 2002
Adaptive test program generation: Planning for the unplanned
- A. Adir
- R. Emek
- et al.
- 2002
- HLDVT 2002