IBM Telum II Microprocessor: 5.5 GHz With On-Die AI and Data Processing, and Design–Technology Co-Optimizations for Power, Area, and Reliability
- Gerald Strevig
- David Wolpert
- et al.
- 2025
- IEEE Journal of Solid State Circuits
Publications
32 results for Matthew Angyal
Identification and sensitivity analysis of a correlated ground rule system (design arc)
- Eric Eastman
- Dureseti Chidambarrao
- et al.
- 2017
- SPIE Advanced Lithography 2017
3Di DC-DC Buck Micro Converter with TSVs, Grind Side Inductors, and Deep Trench Decoupling Capacitors in 32nm SOI CMOS
- J. Safran
- Giri N. K. Rangan
- et al.
- 2016
- ECTC 2016
3D integration ESD protection design and analysis
- Souvick Mitra
- Ephrem Gebreselasie
- et al.
- 2015
- EOS/ESD 2015
Defect mitigation of plasma-induced delamination of TiW/Cu from SiNx layer in thin si interposer processing with glass carriers
- Vijay Sukumaran
- Thuy Tran-Quinn
- et al.
- 2015
- ECTC 2015
An enhanced thermo-compression bonding process to address warpage in 3D integration of large die on organic substrates
- Katsuyuki Sakuma
- Krishna Tunga
- et al.
- 2015
- ECTC 2015
Bonding technologies for chip level and wafer level 3D integration
- Katsuyuki Sakuma
- Spyridon Skordas
- et al.
- 2014
- ECTC 2014
Optimization of Cu damascene electrodeposition process in ULSI for yield and reliability improvement
- Ingrid Shao
- T. Cheng
- et al.
- 2013
- ECS Transactions
Post Cu CMP cleaning process evaluation for 32nm and 22nm technology nodes
- Wei-Tsu Tseng
- Donald Canaperi
- et al.
- 2012
- ASMC 2012
Electromigration in Cu(Al) and Cu(Mn) damascene lines
- C.-K. Hu
- J. Ohm
- et al.
- 2012
- Journal of Applied Physics