Performance impact of through-silicon vias (TSVs) in three-dimensional technology measured by SRAM ring oscillators
- Jente B. Kuang
- Keith A. Jenkins
- et al.
- 2013
- ESSCIRC 2013
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43 results for Kevin G. Stawiasz
1Mb 0.41 μm2 2T-2R cell nonvolatile TCAM with two-bit encoding and clocked self-referenced sensing
- Jing Li
- Robert Montoye
- et al.
- 2013
- VLSI Circuits 2013
1Mb 0.41 μm2 2T-2R cell nonvolatile TCAM with two-bit encoding and clocked self-referenced sensing
- Jing Li
- Robert Montoye
- et al.
- 2013
- VLSI Technology 2013
A DPLL-based per core variable frequency clock generator for an eight-core POWER7™ microprocessor
- Jose Tierno
- Alexander Rylyakov
- et al.
- 2010
- VLSI Circuits 2010
A fully-integrated switched-capacitor 2:1 Voltage converter with regulation capability and 90% efficiency at 2.3A/mm2
- Leland Chang
- Robert K. Montoye
- et al.
- 2010
- VLSI Circuits 2010
On-chip circuit for monitoring frequency degradation due to NBTI
- Kevin Stawiasz
- Keith A. Jenkins
- et al.
- 2008
- IRPS 2008
A sub-600mV, fluctuation tolerant 65nm CMOS SRAM array with dynamic cell biasing
- Azeez Bhavnagarwala
- Stephen Kosonocky
- et al.
- 2007
- VLSI Circuits 2007
Experimental Measurement of A Novel Power Gating Structure with Intermediate Power Saving Mode
- Suhwan Kim
- Stephen V. Kosonocky
- et al.
- 2004
- ISLPED 2004
Experimental measurement of a novel power gating structure with intermediate power saving mode
- Suhwan Kim
- Stephen V. Kosonocky
- et al.
- 2004
- ISLPED 2004
Minimizing inductive noise in system-on-a-chip with multiple power gating structures
- Suhwan Kim
- Stephen V. Kosonocky
- et al.
- 2003
- ESSCIRC 2003