Paul Solomon, Brian A. Bryce, et al.
Nano Letters
This paper describes upsets of 65 nm flip-flops caused by Single-Event-Transients in clock-tree circuits. The upset rate is predicted through modeling, and compared to upset rates measured on a 65 nm test chip with 15 MeV carbon ions and 148 MeV protons. © 2009 IEEE.
Paul Solomon, Brian A. Bryce, et al.
Nano Letters
Keith A. Jenkins, David F. Heidel
Microelectronic Engineering
David F. Heidel, Kenneth P. Rodbell, et al.
IEEE TNS
Michael S. Gordon, Ken Rodbell, et al.
Semiconductor Science and Technology