Designing a testable System on a Chip
- S.V. Kosonocky
- A.A. Bright
- et al.
- 1998
- VTS 1998
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43 results for Kevin G. Stawiasz
High speed serializing/de-serializing design-for-test method for evaluating a 1 GHz microprocessor
- D. Heidel
- S. Dhong
- et al.
- 1998
- VTS 1998
Low cost 10 gigabit/s optical interconnects for parallel processing
- D. Kuchta
- J.D. Crow
- et al.
- 1998
- MPPOI 1998
500 MS/s 10-bit CMOS D/A converter
- Peter Xiao
- John Shin
- et al.
- 1996
- ASICON 1996
High-performance high-yield, uniform 32-channel optical receiver array
- Joong-ho Choi
- D.L. Rogers
- et al.
- 1996
- OFC 1996
Low Energy Proton SEUs in 32-nm SOI SRAMs at Low Vdd
- Ken Rodbell
- Michael S. Gordon
- et al.
- 2017
- IEEE TNS
32 and 45 nm radiation-hardened-by-design (RHBD) SOI latches
- Kenneth P. Rodbell
- David F. Heidel
- et al.
- 2011
- IEEE TNS
Flip-flop upsets from single-event-transients in 65 nm clock circuits
- Larry Wissel
- David F. Heidel
- et al.
- 2009
- IEEE TNS
A sub-600-mV, fluctuation tolerant 65-nm CMOS SRAM array with dynamic cell biasing
- Azeez J. Bhavnagarwala
- Stephen Kosonocky
- et al.
- 2008
- IEEE Journal of Solid-State Circuits
A multi-mode power gating structure for low-voltage deep-submicron CMOS ICs
- Suhwan Kim
- Stephen V. Kosonocky
- et al.
- 2007
- IEEE TCAS-II