Koushik K. Das, Rajiv V. Joshi, et al.
ESSCIRC 2003
A multiple power domain strategy in which each power domain has an independent power gating structure is an effective means for reducing leakage power consumption in a system-on-a-chip. During an individual power gating structure power-mode transition, however, serious inductive noise is introduced that may affect normal operation of neighboring circuits. We present a novel power gating structure in which inductive noise is reduced through gradual turn-on and turn-off its sleep transistor. Experimental simulation results with PowerSpice fixtured in different package models demonstrate the effectiveness of the proposed power gate switching noise reduction technique. © 2003 IEEE.
Koushik K. Das, Rajiv V. Joshi, et al.
ESSCIRC 2003
Suhwan Kim, Conrad H. Ziesler, et al.
IEEE Transactions on VLSI Systems
Visvesh Sathe, Conrad Ziesler, et al.
SOCC 2004
C.H. Ziesler, Joohee Kim, et al.
SOCC 2003