A 1.3 GSample/s 10-tap full-rate variable latency self-timed FIR filter with clocked interfaces
- Jose Tierno
- Alexander Rylyakov
- et al.
- 2002
- ISSCC 2002
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156 results for Alexander V. Rylyakov
A 1.3 Gsample/s 10-tap full-rate variable-latency self-timed FIR filter with clocked interfaces
- Jose Tierno
- Alexander Rylyakov
- et al.
- 2002
- ISSCC 2002
50 Gb/s SiGe BiCMOS 4:1 multiplexer and 1:4 demultiplexer for serial communication systems
- Mounir Meghelli
- Alexander V. Rylyakov
- et al.
- 2002
- ISSCC 2002
50 Gb/s SiGe BiCMOS 4:1 multiplexer and 1:4 demultiplexer for serial-communication systems
- Mounir Meghelli
- Alexander V. Rylyakov
- et al.
- 2002
- ISSCC 2002
A 2.3GSample/s 10-tap digital FIR filter for magnetic recording read channels
- S. Rylov
- A. Rylyakov
- et al.
- 2001
- ISSCC 2001
A 25 Gb/s Burst-Mode Receiver for Low Latency Photonic Switch Networks
- Alexander V. Rylyakov
- Jonathan E. Proesel
- et al.
- 2015
- IEEE JSSC
A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology
- Timothy O. Dickson
- Yong Liu
- et al.
- 2015
- IEEE JSSC
A 28 GHz hybrid PLL in 32 nm SOI CMOS
- Mark Ferriss
- Alexander Rylyakov
- et al.
- 2014
- IEEE JSSC
A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing
- Bodhisatwa Sadhu
- Mark A. Ferriss
- et al.
- 2013
- IEEE JSSC
An integral path self-calibration scheme for a dual-loop PLL
- Mark Ferriss
- Jean-Olivier Plouchart
- et al.
- 2013
- IEEE JSSC