High performance UTBB FDSOI devices featuring 20nm gate length for 14nm node and beyond
- Q. Liu
- M. Vinet
- et al.
- 2013
- IEDM 2013
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37 results for L.F. Edge
High performance extremely thin SOI (ETSOI) hybrid CMOS with Si channel NFET and strained SiGe channel PFET
- K. Cheng
- A. Khakifirooz
- et al.
- 2012
- IEDM 2012
Assessment of fully-depleted planar CMOS for low power complex circuit operation
- Zhibin Ren
- S. Mehta
- et al.
- 2011
- IEDM 2011
A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications
- S. Krishnan
- U. Kwon
- et al.
- 2011
- IEDM 2011
Physical origin of pFET threshold voltage modulation by ge channel ion implantation (GC-I/I)
- Yoshinori Tsuchiya
- Nathaniel Berliner
- et al.
- 2010
- IEDM 2010
Extremely thin SOI (ETSOI) CMOS with record low variability for low power system-on-chip applications
- K. Cheng
- A. Khakifirooz
- et al.
- 2009
- IEDM 2009
22 nm technology compatible fully functional 0.1 μm 2 6T-sram cell
- B. Haran
- A. Kumar
- et al.
- 2008
- IEDM 2008
Hole transport in strained and relaxed sige channel extremely thin SOI MOSFETs
- Ali Khakifirooz
- Kangguo Cheng
- et al.
- 2013
- IEEE Electron Device Letters
High-performance partially depleted SOI PFETs with in situ doped sige raised source/drain and implant-free extension
- Ali Khakifirooz
- Kangguo Cheng
- et al.
- 2011
- IEEE Electron Device Letters
A novel low resistance gate fill for extreme gate length scaling at 20nm and beyond for gate-last high-k/metal gate CMOS technology
- U. Kwon
- K. Wong
- et al.
- 2012
- VLSI Technology 2012