Lithographic qualification of new opaque MoSi binary mask blank for the 32-nm node and beyond
- Greg McIntyre
- Michael Hibbs
- et al.
- 2010
- J. Micro/Nanolithogr. MEMS MOEMS
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49 results for Scott D. Halle
SMO photomask inspection in the lithographic plane
- Emily Gallagher
- Karen Badger
- et al.
- 2009
- SPIE Photomask Technology + EUV Lithography 2009
22 nm technology node active layer patterning for planar transistor devices
- Ryoung-Han Kim
- Steven Holmes
- et al.
- 2009
- SPIE Advanced Lithography 2009
Experimental result and simulation analysis for the use of pixelated illumination from source mask optimization for 22nm logic lithography process
- Kafai Lai
- Alan E. Rosenbluth
- et al.
- 2009
- SPIE Advanced Lithography 2009
Combinatorial overlay control for double patterning
- Christopher P. Ausschnitt
- Scott D. Halle
- 2009
- Journal of Micro/Nanolithography, MEMS, and MOEMS
22 nm technology compatible fully functional 0.1 μm 2 6T-sram cell
- B. Haran
- A. Kumar
- et al.
- 2008
- IEDM 2008
32 NM Logic patterning options with immersion lithography
- K. Lai
- S. Burns
- et al.
- 2008
- SPIE Advanced Lithography 2008
Paving the way to a full chip gate level double patterning application
- Henning Haffner
- Jason Meiring
- et al.
- 2007
- SPIE Photomask Technology + EUV Lithography 2007
Patterning strategies for gate level tip-tip distance reduction in SRAM cell for 45nm and beyond
- Haoren Zhuang
- Helen Wang
- et al.
- 2007
- ISTC 2007
Mastering double exposure process window aware OPC by means of virtual targets
- Henning Haffner
- Zachary Baum
- et al.
- 2006
- SPIE Photomask Technology 2006