High performance 14nm SOI FinFET CMOS technology with 0.0174μm2 embedded DRAM and 15 levels of Cu metallization
- C.-H.C-H. Lin
- Brian Greene
- et al.
- 2014
- IEDM 2014
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19 results for Fernando Guarin
32nm general purpose bulk CMOS technology for high performance applications at low voltage
- F. Arnaud
- J. Liu
- et al.
- 2008
- IEDM 2008
65nm CMOS technology for low power applications
- A. Steegen
- R. Mo
- et al.
- 2005
- IEDM 2005
High-performance sub-0.08 μm CMOS with dual gate oxide and 9.7 ps inverter delay
- M. Hargrove
- S.W. Crowder
- et al.
- 1998
- IEDM 1998
Electrical characteristics and reliability of sub-3 nm gate oxides grown on nitrogen implanted silicon substrates
- L.K. Han
- S.W. Crowder
- et al.
- 1997
- IEDM 1997
Experimental and Simulation Results of Magnetic Modulation of Gate Oxide Tunneling Current in Nanoscaled MOS Transistors
- Gabriela A. Rodríguez-Ruiz
- Edmundo A. Gutiérrez-Domínguez
- et al.
- 2015
- IEEE Electron Device Letters
Observation of asymmetric magnetoconductance in strained 28-nm Si MOSFETs
- E.A. Gutiérrez-D.
- E. Póndigo-De Los A.
- et al.
- 2012
- IEEE Electron Device Letters
Layout dependence of gate dielectric TDDB in HKMG FinFET technology
- Wen Liu
- Ernest Y. Wu
- et al.
- 2016
- IRPS 2016
Non-homogeneous space mechanical strain induces asymmetrical magneto-tunneling conductance in MOSFETs
- A. Erika Póndigo De Los
- Edmundo A. Gutierrez-D
- et al.
- 2014
- ESSDERC 2014
Process dependence of AC/DC PBTI in HKMG n-MOSFETs
- Wen Liu
- Giuseppe La Rosa
- et al.
- 2014
- IRPS 2014