High performance 14nm SOI FinFET CMOS technology with 0.0174μm2 embedded DRAM and 15 levels of Cu metallization
- C.-H.C-H. Lin
- Brian Greene
- et al.
- 2014
- IEDM 2014
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15 results for U. Kwon
Replacement metal gate resistance in FinFET architecture modelling, validation and extendibility
- Ruqiang Bao
- Brian Greene
- et al.
- 2015
- IEDM 2015
A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications
- S. Krishnan
- U. Kwon
- et al.
- 2011
- IEDM 2011
Stress liner proximity technique to enhance carrier mobility in high-κ metal gate MOSFETs
- Dechao Guo
- Kathryn Schonenberg
- et al.
- 2009
- MRS Fall Meeting 2009
Gate length scaling and high drive currents enabled for high performance SOI technology using high-κ/metal gate
- K. Henson
- H. Bu
- et al.
- 2008
- IEDM 2008
An Analytical Metal Resistance Model and Its Application for Sub-22-nm Metal-Gate CMOS
- X. Miao
- Ruqiang Bao
- et al.
- 2015
- IEEE Electron Device Letters
Process optimizations for NBTI/PBTI for future replacement metal gate technologies
- Barry P. Linder
- A. Dasgupta
- et al.
- 2016
- IRPS 2016
Simple Gate Metal Anneal (SIGMA) stack for FinFET Replacement Metal Gate toward 14nm and beyond
- Takashi Ando
- B. Kannan
- et al.
- 2014
- VLSI Technology 2014
Deposited ALD SiO2 high-k/metal gate interface for high voltage analog and I/O devices on next generation alternative channels and FINFET device structures
- S. Siddiqui
- M.M. Chowdhury
- et al.
- 2013
- ECS Meeting 2013
Intrinsic dielectric stack reliability of a high performance bulk planar 20nm replacement gate high-k metal gate technology and comparison to 28nm gate first high-k metal gate process
- W. McMahon
- C. Tian
- et al.
- 2013
- IRPS 2013