A 1.8 pJ/bit 16 × 16Gb/s source-synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration
- Timothy O. Dickson
- Yong Liu
- et al.
- 2016
- IEEE JSSC
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46 results for Benjamin D. Parker
A 25Gb/s ADC-based serial line receiver in 32nm CMOS SOI
- Sergey V. Rylov
- Troy Beukema
- et al.
- 2016
- ISSCC 2016
A 25 Gb/s Burst-Mode Receiver for Low Latency Photonic Switch Networks
- Alexander V. Rylyakov
- Jonathan E. Proesel
- et al.
- 2015
- IEEE JSSC
A 1.8-pJ/bit 16x16-Gb/s source synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration
- Timothy O. Dickson
- Yong Liu
- et al.
- 2015
- CICC 2015
A 18mW, 3.3dB NF, 60GHz LNA in 32nm SOI CMOS technology with autonomic NF calibration
- Jean-Olivier Plouchart
- Fa Wang
- et al.
- 2015
- RFIC 2015
A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology
- Timothy O. Dickson
- Yong Liu
- et al.
- 2015
- IEEE JSSC
W-band dual-polarization phased-array transceiver front-end in SiGe BiCMOS
- Arun Natarajan
- Alberto Valdes-Garcia
- et al.
- 2015
- IEEE T-MTT
A 25Gb/s burst-mode receiver for rapidly reconfigurable optical networks
- Alexander V. Rylyakov
- Jonathan E. Proesel
- et al.
- 2015
- ISSCC 2015
A 1.4-pJ/b, power-scalable 16×12-Gb/s source-synchronous I/O with DFE receiver in 32nm SOI CMOS technology
- Timothy O. Dickson
- Yong Liu
- et al.
- 2014
- CICC 2014
A compact 4-chip package with 64 embedded dual-polarization antennas for W-band phased-array transceivers
- Xiaoxiong Gu
- Duixian Liu
- et al.
- 2014
- ECTC 2014