Sub-picosecond jitter SiGe BiCMOS transmit and receive PLLs for 12.5 Gbaud serial data communication
- D. Friedman
- M. Meghelli
- et al.
- 2000
- VLSI Circuits 2000
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46 results for Benjamin D. Parker
Designing a testable System on a Chip
- S.V. Kosonocky
- A.A. Bright
- et al.
- 1998
- VTS 1998
W-band dual-polarization phased-array transceiver front-end in SiGe BiCMOS
- Arun Natarajan
- Alberto Valdes-Garcia
- et al.
- 2015
- IEEE T-MTT
Indirect performance sensing for on-chip self-healing of analog and RF circuits
- Shupeng Sun
- Fa Wang
- et al.
- 2014
- IEEE TCAS-I
Adaptive circuit design methodology and test applied to millimeter-wave circuits
- Jean-Olivier Plouchart
- Benjamin Parker
- et al.
- 2014
- IEEE Design and Test
Integrated self-healing for mm-wave power amplifiers
- Steven M. Bowers
- Kaushik Sengupta
- et al.
- 2013
- IEEE T-MTT
A 23.5 GHz PLL with an adaptively biased VCO in 32 nm SOI-CMOS
- Jean-Olivier Plouchart
- Mark A. Ferriss
- et al.
- 2013
- IEEE TCAS-I
An 8x 10-Gb/s source-synchronous I/O system based on high-density silicon carrier interconnects
- Timothy O. Dickson
- Yong Liu
- et al.
- 2012
- IEEE Journal of Solid-State Circuits
A 10-Gb/s 5-tap DFE/4-tap FFE transceiver in 90-nm CMOS technology
- John F. Bulzacchelli
- Mounir Meghelli
- et al.
- 2006
- IEEE Journal of Solid-State Circuits
A 6.4-Gb/s CMOS SerDes core with feed-forward and decision-feedback equalization
- Troy Beukema
- Michael Sorna
- et al.
- 2005
- IEEE Journal of Solid-State Circuits