A compact eFUSE programmable array memory for SOI CMOS
- John Safran
- Alan Leslie
- et al.
- 2007
- VLSI Circuits 2007
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34 results for Toshiaki Kirihata
Electrically Programmable Fuse (eFUSE): From Memory Redundancy to Autonomic Chips
- Norm Robson
- John Safran
- et al.
- 2007
- CICC 2007
A 0.168μm 2/0.11μm 2 highly scalable high performance embedded DRAM cell for 90/65-nm logic applications
- G. Wang
- P. Parries
- et al.
- 2005
- VLSI Technology 2005
Embedded dynamic random access memory
- Toshiaki Kirihata
- 2003
- VLSI-TSA 2003
Destructive-read Random Access Memory System Buffered with Destructive-read Memory Cache for SoC Applications
- Brian L. Ji
- Seiji Munetoh
- et al.
- 2003
- VLSI Circuits 2003
Challenges of Aluminum RIE Technology at sub 0.45 μm Pitches
- R. Ravikumar
- R. Filippi
- et al.
- 1999
- IITC 1999
Development of a high bandwidth merged logic/DRAM multimedia chip
- W.K. Luk
- Y. Katayama
- et al.
- 1997
- ICCD 1997
Flexible test mode design for DRAM characterization
- H. Wong
- T. Kirihata
- et al.
- 1996
- VLSI Circuits 1996
Experimental 27 ns 1 Mb CMOS high-speed DRAM
- S. Dhong
- W.H. Henkels
- et al.
- 1989
- VLSI Circuits 1989
Three-Dimensional Dynamic Random Access Memories Using Through-Silicon-Vias
- Toshiaki Kirihata
- John Golz
- et al.
- 2016
- IEEE JESTCS