A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier
- John Barth
- William R. Reohr
- et al.
- 2008
- IEEE Journal of Solid-State Circuits
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34 results for Toshiaki Kirihata
A compact eFUSE programmable array memory for SOI CMOS
- John Safran
- Alan Leslie
- et al.
- 2007
- VLSI Circuits 2007
Electrically Programmable Fuse (eFUSE): From Memory Redundancy to Autonomic Chips
- Norm Robson
- John Safran
- et al.
- 2007
- CICC 2007
A 500MHz random cycle 1.5ns-latency, SOI embedded DRAM macro featuring a 3T micro sense amplifier
- John Barth
- William Reohr
- et al.
- 2007
- ISSCC 2007
A 0.127 μm2 high performance 65 nm SOI based embedded DRAM for on-processor applications
- G. Wang
- K. Cheng
- et al.
- 2006
- IEDM 2006
A 0.168μm 2/0.11μm 2 highly scalable high performance embedded DRAM cell for 90/65-nm logic applications
- G. Wang
- P. Parries
- et al.
- 2005
- VLSI Technology 2005
Embedded dynamic random access memory
- Toshiaki Kirihata
- 2003
- VLSI-TSA 2003
Destructive-read Random Access Memory System Buffered with Destructive-read Memory Cache for SoC Applications
- Brian L. Ji
- Seiji Munetoh
- et al.
- 2003
- VLSI Circuits 2003
A 7F2 cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4-Gb DRAM's
- Heinz Hoenigschmid
- Alexander Frey
- et al.
- 2000
- IEEE Journal of Solid-State Circuits
Challenges of Aluminum RIE Technology at sub 0.45 μm Pitches
- R. Ravikumar
- R. Filippi
- et al.
- 1999
- IITC 1999