Experiment and model for deviation from Pelgrom scaling relation in device width
- Ning Lu
- J. Brown
- et al.
- 2014
- IEDM 2014
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32 results for Richard A. Wachnik
Off-state self-heating, micro-hot-spots, and stress-induced device considerations in scaled technologies
- Siyu Koswatta
- N. Mavilla
- et al.
- 2015
- IEDM 2015
New layout dependency in high-k/metal gate MOSFETs
- M. Hamaguchi
- Deleep R. Nair
- et al.
- 2011
- IEDM 2011
(110) Channel, SiON gate-dielectric PMOS with record high Ion=1 mA/μm through channel stress and source drain external resistance (R ext) engineering
- B. Yang
- A. Waite
- et al.
- 2007
- IEDM 2007
High performance 45-nm SOI technology with enhanced strain, porous low-k BEOL, and immersion lithography
- S. Narasimha
- K. Onishi
- et al.
- 2006
- IEDM 2006
Full copper wiring in a sub-0.25 μm CMOS ULSI technology
- D. Edelstein
- J. Heidenreich
- et al.
- 1997
- IEDM 1997
An Analytical Metal Resistance Model and Its Application for Sub-22-nm Metal-Gate CMOS
- X. Miao
- Ruqiang Bao
- et al.
- 2015
- IEEE Electron Device Letters
Efficient and accurate schematic transistor model of FinFET parasitic elements
- Ning Lu
- Terence B. Hook
- et al.
- 2013
- IEEE Electron Device Letters
Symmetry breaking in the drain current of multi-finger transistors
- Ning Lu
- Sungjae Lee
- et al.
- 2015
- CICC 2015
Modeling of resistance in FinFET local interconnect
- Ning Lu
- Pooja M. Kotecha
- et al.
- 2014
- CICC 2014