Optimizing history effects in 65nm PD-SOI CMOS
- Q. Liang
- T. Kawamura
- et al.
- 2006
- IEEE International SOI Conference 2006
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16 results for Kevin McStay
High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell
- E. Leobandung
- H. Nayakama
- et al.
- 2005
- VLSI Technology 2005
Body voltage and history effect sensitivity to key device parameters in 90nm PD-SOI
- S. Kawanaka
- M.B. Ketchen
- et al.
- 2004
- IEEE International SOI Conference 2004
Super-halo asymmetric vertical pass transistor design for ultra-dense DRAM technologies
- D. Chidambarrao
- K. McStay
- et al.
- 2003
- VLSI-TSA 2003
On the retention time distribution of dual-channel vertical DRAM technologies
- J. Beintner
- Y. Li
- et al.
- 2003
- VLSI-TSA 2003
Transistor Matching and Fin Angle Variation in FinFET Technology
- Samarth Agarwal
- Terence B. Hook
- et al.
- 2015
- IEEE T-ED