Strained-Si Devices and Circuits for Low-Power Applications
- Keunwoo Kim
- Rajiv V. Joshi
- et al.
- 2003
- ISLPED 2003
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79 results for Keunwoo Kim
Design considerations of scaled sub-0.1 μm PD/SOI CMOS circuits
- C.T. Chuang
- R.V. Joshi
- et al.
- 2003
- ISQED 2003
Performance assessment of scaled strained-Si channel-on-insulator (SSOI) CMOS
- Keunwoo Kim
- Ching-Te Chuang
- et al.
- 2002
- IEEE International SOI Conference 2002
Super fast physics-based methodology for accurate memory yield prediction
- Rajiv V. Joshi
- Keunwoo Kim
- et al.
- 2015
- IEEE Transactions on VLSI Systems
Assessment of structure variation in silicon nanowire FETs and impact on SRAM
- Yi-Bo Liao
- Meng-Hsueh Chiang
- et al.
- 2012
- Microelectronics Journal
TCAD/physics-based analysis of high-density dual-BOX FD/SOI SRAM cell with improved stability
- Keunwoo Kim
- Jente B. Kuang
- et al.
- 2009
- IEEE Transactions on Electron Devices
Selective device structure scaling and parasitics engineering: A way to extend the technology roadmap
- Lan Wei
- Jie Deng
- et al.
- 2009
- IEEE Transactions on Electron Devices
Circuit techniques utilizing independent gate control in double-gate technologies
- Jente B. Kuang
- Keunwoo Kim
- et al.
- 2008
- IEEE Transactions on VLSI Systems
An on-chip test structure and digital measurement method for statistical characterization of local random variability in a process
- Saibal Mukhopadhyay
- Keunwoo Kim
- et al.
- 2008
- IEEE Journal of Solid-State Circuits
Optimal design of triple-gate devices for high-performance and low-power applications
- Meng-Hsueh Chiang
- Jeng-Nan Lin
- et al.
- 2008
- IEEE Transactions on Electron Devices