Asymmetrical triple-gate FET
Meng-Hsueh Chiang, Jeng-Nan Lin, et al.
SISPAD 2007
In this letter, the random dopant fluctuation effect in ultrathin-body (UTB) fully depleted/silicon-on-insulator (FD/SOI) devices is analyzed. We show that due to larger variability and asymmetry in threshold voltage Vt distribution, it will be difficult to use UTB FD/ SOI devices for sub-50-nm static random access memory (SRAM) design. Using thinner buried oxide (BOX) FD/SOI devices, the asymmetry in the Vt spread can be reduced. We present a viable concept of FD/ SOI SRAM and predict that a thin-BOX device is the optimal FD/SOI structure for SRAM in sub-50-nm technology nodes. © 2006 IEEE.
Meng-Hsueh Chiang, Jeng-Nan Lin, et al.
SISPAD 2007
Xinlin Wang, Phil Oldiges, et al.
SISPAD 2005
Shu-Jen Han, Dechao Guo, et al.
IEEE Electron Device Letters
Keunwoo Kim, Koushik K. Das, et al.
IEEE Transactions on Electron Devices