High performance UTBB FDSOI devices featuring 20nm gate length for 14nm node and beyond
- Q. Liu
- M. Vinet
- et al.
- 2013
- IEDM 2013
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14 results for Q. Liu
High performance extremely thin SOI (ETSOI) hybrid CMOS with Si channel NFET and strained SiGe channel PFET
- K. Cheng
- A. Khakifirooz
- et al.
- 2012
- IEDM 2012
Hole transport in strained and relaxed sige channel extremely thin SOI MOSFETs
- Ali Khakifirooz
- Kangguo Cheng
- et al.
- 2013
- IEEE Electron Device Letters
Scalability of extremely thin SOI (ETSOI) MOSFETs to sub-20-nm gate length
- Ali Khakifirooz
- Kangguo Cheng
- et al.
- 2012
- IEEE Electron Device Letters
Impact of source/drain silicon cap on FDSOI SiGe pMOSFET performance
- E. Augendre
- S. Maitrejean
- et al.
- 2015
- S3S 2015
Device design considerations for next generation CMOS technology: Planar FDSOI and FinFET (Invited)
- Bruce Doris
- Kangguo Cheng
- et al.
- 2013
- VLSI-TSA 2013
Development of KrF hybrid resist for a dual isolation application
- Sen Liu
- Steven Holmes
- et al.
- 2013
- SPIE Advanced Lithography 2013
Strain engineered extremely thin SOI (ETSOI) for high-performance CMOS
- A. Khakifirooz
- Kangguo Cheng
- et al.
- 2012
- VLSI Technology 2012
Impact of substrate bias on GIDL for thin-BOX ETSOI devices
- Pranita Kulkarni
- Q. Liu
- et al.
- 2011
- SISPAD 2011
ETSOI CMOS for system-on-chip applications featuring 22nm gate length, sub-100nm gate pitch, and 0.08μm2 SRAM cell
- Kangguo Cheng
- A. Khakifirooz
- et al.
- 2011
- VLSI Technology 2011