Effect of embedded-sige eSiGeon ESD TLP and VFTLP characteristics of diode-triggered silicon controlled rectifiers DTSCRs
- Rahul Mishra
- Junjun Li
- et al.
- 2012
- EOS/ESD 2012
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35 results for Robert Gauthier
Technology scaling effects on the ESD performance of silicide-blocked PMOSFET devices in nanometer bulk CMOS technologies
- Junjun Li
- Rahul Mishra
- et al.
- 2011
- EOS/ESD 2011
Pulsed gate dielectric breakdown in a 32 nm technology under different ESD stress configurations
- Yang Yang
- Robert Gauthier
- et al.
- 2010
- EOS/ESD 2010
Predictive full circuit ESD simulation and analysis using extended ESD compact models: Methodology and tool implementation
- Junjun Li
- Robert Gauthier
- et al.
- 2010
- EOS/ESD 2010
Characterization of high-k/metal gate stack breakdown in the time scale of ESD events
- Yang Yang
- James Di Sarro
- et al.
- 2010
- IRPS 2010
Technology scaling of advanced bulk CMOS on-chip ESD protection down to the 32nm node
- Junjun Li
- Kiran Chatty
- et al.
- 2009
- EOS/ESD 2009
ESD time-domain characterization of high-k gate dielectric in a 32 nm CMOS technology
- James Di Sarro
- Yang Yang
- et al.
- 2009
- EOS/ESD 2009
Capacitance investigation of diodes and SCRs for ESD protection of high frequency circuits in sub-100nm bulk CMOS technologies
- Junjun Li
- Robert Gauthier
- et al.
- 2007
- EOS/ESD 2007
Failure analysis of I/O with ESD protection devices in advanced CMOS technologies
- Mujahid Muhammad
- Robert Gauthier
- et al.
- 2007
- IPFA 2007
Evaluation of SCR-based ESD protection devices in 90nm and 65nm CMOS technologies
- James Di Sarro
- Kiran Chatty
- et al.
- 2007
- IRPS 2007