Design and optimization of ESD lateral NPN device in 14nm Fin FET SOI CMOS technology
- You Li
- Rahul Mishra
- et al.
- 2015
- EOS/ESD 2015
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35 results for Robert Gauthier
3D integration ESD protection design and analysis
- Souvick Mitra
- Ephrem Gebreselasie
- et al.
- 2015
- EOS/ESD 2015
ESD device performance analysis in a 14nm Fin FET SOI CMOS technology: Fin-based versus planar-based
- Junjun Li
- Robert Gauthier
- et al.
- 2014
- EOS/ESD 2014
Junction engineering for SOI SCR triggering and performance improvement
- You Li
- Junjun Li
- et al.
- 2014
- EOS/ESD 2014
Reflection control in VF-TLp systems
- Evan Grund
- Thomas Chang
- et al.
- 2014
- EOS/ESD 2014
Maximizing ESD robustness of current-mode-logic (CML) driver with internal gate bias network
- You Li
- James Di Sarro
- et al.
- 2013
- EOS/ESD 2013
Influence of package parasitic elements on CDM stress
- James Di Sarro
- Bill Reynold
- et al.
- 2013
- EOS/ESD 2013
Investigation of SOI SCR triggering and current sustaining under DC and TLP conditions
- Junjun Li
- James Di Sarro
- et al.
- 2013
- EOS/ESD 2013
Design and optimization of scr devices for on-chip esd protection in advanced SOI CMOS technologies
- Junjun Li
- James Di Sarro
- et al.
- 2012
- EOS/ESD 2012
Effect of embedded-sige eSiGeon ESD TLP and VFTLP characteristics of diode-triggered silicon controlled rectifiers DTSCRs
- Rahul Mishra
- Junjun Li
- et al.
- 2012
- EOS/ESD 2012