Post Cu CMP cleaning process evaluation for 32nm and 22nm technology nodes
- Wei-Tsu Tseng
- Donald Canaperi
- et al.
- 2012
- ASMC 2012
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26 results for X. Chen
CoWP metal caps for reliable 32 nm 1X Cu interconnects in porous ULK (k=2.4)
- E. Huang
- M. Oh
- et al.
- 2009
- ADMETA 2009
High-κ/metal gate low power bulk technology - Performance evaluation of standard CMOS logic circuits, microprocessor critical path replicas, and SRAM for 45nm and beyond
- D.-G. Park
- K. Stein
- et al.
- 2009
- VLSI-TSA 2009
Reduction of RTA-driven intra-die variation via model-based layout optimization
- J.C. Scott
- O. Gluschenkov
- et al.
- 2009
- VLSI Technology 2009
Developing contact oxide CUP process for 32 nm technology nodes
- John H. Zhang
- Rajasekhar Venigalla
- et al.
- 2008
- VMIC 2008
A cost effective 32nm high-K/metal gate CMOS technology for low power applications with single-metal/gate-first process
- X. Chen
- S. Samavedam
- et al.
- 2008
- VLSI Technology 2008
Effect of end-of-range defects on device leakage in direct silicon bonded (DSB) technology
- Haizhou Yin
- M. Hamaguchi
- et al.
- 2008
- VLSI-TSA 2008
Scalability of Direct Silicon Bonded (DSB) technology for 32nm node and beyond
- Haizhou Yin
- C.Y. Sung
- et al.
- 2007
- VLSI Technology 2007
CMOS fabricated by hybrid-orientation technology (HOT)
- Bin Yang
- M. Yang
- et al.
- 2007
- IEDST 2007
Lower resistance scaled metal contacts to silicide for advanced CMOS
- A. Topol
- C. Sheraw
- et al.
- 2006
- VLSI Technology 2006