0.026μm2 high performance Embedded DRAM in 22nm technology for server and SOC applications
- C. Pei
- G. Wang
- et al.
- 2014
- IEDM 2014
Publications
Date
Featured collections
Popular topics
26 results for X. Chen
Cu CMP and its challenge for 20nm nodes and beyond
- John H. Zhang
- Wei-Tsu Tseng
- et al.
- 2012
- MRS Spring Meeting 2012
A novel low resistance gate fill for extreme gate length scaling at 20nm and beyond for gate-last high-k/metal gate CMOS technology
- U. Kwon
- K. Wong
- et al.
- 2012
- VLSI Technology 2012
High performance bulk planar 20nm CMOS technology for low power mobile applications
- Huiling Shang
- Sameer Jain
- et al.
- 2012
- VLSI Technology 2012
Post Cu CMP cleaning process evaluation for 32nm and 22nm technology nodes
- Wei-Tsu Tseng
- Donald Canaperi
- et al.
- 2012
- ASMC 2012
Optimizing stressor film deposition sequence in polish rate order for best planarization
- John H. Zhang
- Changyong Xiao
- et al.
- 2011
- MRS Spring Meeting 2011
CoWP metal caps for reliable 32 nm 1X Cu interconnects in porous ULK (k=2.4)
- E. Huang
- M. Oh
- et al.
- 2009
- ADMETA 2009
High-κ/metal gate low power bulk technology - Performance evaluation of standard CMOS logic circuits, microprocessor critical path replicas, and SRAM for 45nm and beyond
- D.-G. Park
- K. Stein
- et al.
- 2009
- VLSI-TSA 2009
Reduction of RTA-driven intra-die variation via model-based layout optimization
- J.C. Scott
- O. Gluschenkov
- et al.
- 2009
- VLSI Technology 2009
Developing contact oxide CUP process for 32 nm technology nodes
- John H. Zhang
- Rajasekhar Venigalla
- et al.
- 2008
- VMIC 2008