Performance enhancement on sub-70 nm strained silicon SOI MOSFETS on ultra-thin thermally mixed strained silicon/SiGe on insulator(TM-SGOI) substrate with raised S/D
- B.H. Lee
- A.C. Mocuta
- et al.
- 2002
- IEDM 2002
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49 results for P. Agnello
A high performance 90 nm SOI technology with 0.992 μm2 6T-SRAM cell
- Mukesh Khare
- S. Ku
- et al.
- 2002
- IEDM 2002
Sub-60 nm physical gate length SOI CMOS
- I.Y. Yang
- K. Chen
- et al.
- 1999
- IEDM 1999
A High-Density 6.9 sq. pm Embedded SRAM Cell in a High-Performance 0.25 μm-Generation CMOS Logic Technology
- S. Subbanna
- P. Agnello
- et al.
- 1996
- IEDM 1996
Submicron CMOS Gate Electrode Discontinuity: Electrical Signature and Effect on Circuit Speed
- Keith A. Jenkins
- J.N. Burghartz
- et al.
- 1993
- IEDM 1993
Mixed Schottky/p-n junction behavior in diodes produced by outdiffusion from polycrystalline cobalt disilicide
- D.P. Foty
- H.I. Hanafi
- et al.
- 1992
- IEDM 1992
High transconductance 0.1 μ m pMOSFET
- Y. Taur
- S. Cohen
- et al.
- 1992
- IEDM 1992
Characterization of devices fabricated in films grown at low temperature by atmospheric pressure CVD
- T.O. Sedgwick
- V.P. Kesan
- et al.
- 1991
- IEDM 1991
Experimental 0.1-um p-Channel MOSFET with p+-Polysilicon Gate on 35-A Gate Oxide
- Yuan Taur
- S. Cohen
- et al.
- 1993
- IEEE Electron Device Letters
22nm technology yield optimization using multivariate 3D virtual fabrication
- B. Cipriany
- B. Jagannathan
- et al.
- 2013
- SISPAD 2013