High performance 32nm SOI CMOS with high-k/metal gate and 0.149μm 2 SRAM and ultra low-k back end with eleven levels of copper
- B. Greene
- Q. Liang
- et al.
- 2009
- VLSI Technology 2009
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18 results for Brian Greene
Extending dual stress liner process to high performance 32nm node SOI CMOS manufacturing
- M. Cai
- B. Greene
- et al.
- 2008
- IEEE International SOI Conference 2008
SMT and enhanced SPT with Recessed SD to improve CMOS Device Performance
- S. Fang
- S.S. Tan
- et al.
- 2008
- ICSICT 2008
Recent progress and challenges in enabling embedded Si:C technology
- B. Yang
- Z. Ren
- et al.
- 2008
- ECS Meeting 2008
Integration of local stress techniques with strained-Si directly on insulator (SSDOI) substrates
- Haizhou Yin
- Z. Ren
- et al.
- 2006
- VLSI Technology 2006
Impact of technology scaling in sub-100 nm nMOSFETs on total-dose radiation response and hot-carrier reliability
- Rajan Arora
- Zachary E. Fleetwood
- et al.
- 2014
- IEEE TNS
Stress liner effects for 32-nm SOI MOSFETs with HKMG
- Ming Cai
- Karthik Ramani
- et al.
- 2010
- IEEE T-ED
Mechanism of solid phase crystallization of prepatterned nanoscale α-Si pillars
- Hyun-Jin Cho
- Brian J. Greene
- et al.
- 2007
- Journal of Applied Physics