High performance 14nm SOI FinFET CMOS technology with 0.0174μm2 embedded DRAM and 15 levels of Cu metallization
- C.-H.C-H. Lin
- Brian Greene
- et al.
- 2014
- IEDM 2014
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9 results for C. DeWan
2nd Generation dual-channel optimization with cSiGe for 22nm HP technology and beyond
- C. Ortolland
- Daniel Jaeger
- et al.
- 2013
- IEDM 2013
22nm High-performance SOI technology featuring dual-embedded stressors, Epi-Plate High-K deep-trench embedded DRAM and self-aligned Via 15LM BEOL
- S. Narasimha
- P. Chang
- et al.
- 2012
- IEDM 2012
Single wafer cleaning lessons in advanced node gate module development
- David F. Hilscher
- Daniel Jaeger
- et al.
- 2013
- ASMC 2013
High-performance high-κ/metal gates for 45nm CMOS and beyond with gate-first processing
- M. Chudzik
- B. Doris
- et al.
- 2007
- VLSI Technology 2007
A high performance 0.13 μm copper BEOL technology with low-k dielectric
- R.D. Goldblatt
- B.N. Agarwala
- et al.
- 2000
- IITC 2000
Integration of copper and fluorosilicate glass for 0.18 μm interconnections
- E. Barth
- T. Ivers
- et al.
- 2000
- IITC 2000
0.18 μm high-performance logic technology
- S.W. Crowder
- S. Greco
- et al.
- 1999
- VLSI Technology 1999
Extension of 248 nm optical lithography: A thin film imaging approach
- Qinghuang Lin
- Ahmad D. Katnani
- et al.
- 1998
- Microlithography 1998