High performance 14nm SOI FinFET CMOS technology with 0.0174μm2 embedded DRAM and 15 levels of Cu metallization
- C.-H.C-H. Lin
- Brian Greene
- et al.
- 2014
- IEDM 2014
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4 results for S. Jain
High performance bulk planar 20nm CMOS technology for low power mobile applications
- Huiling Shang
- Sameer Jain
- et al.
- 2012
- VLSI Technology 2012
Exploring MOL design options for a 20nm CMOS technology using TCAD
- Andreas Scholze
- Stephen Furkay
- et al.
- 2011
- SISPAD 2011
Modeling gate-pitch scaling impact on stress-induced mobility and external resistance for 20nm-node MOSFETs
- Seong-Dong Kim
- Sameer Jain
- et al.
- 2010
- SISPAD 2010